1. Field of the Invention
The present invention relates to a read-out amplifier circuit for a dynamic MOS memory, in which two circuit arms, each composed of a switching transistor and a load transistor, are fed back in that the connection point of the switching transistor and the load transistor in each arm is connected to the control electrode of the switching transistor in the other arm. The connection point of each arm is connected to a sub-portion of a bit line and the connection points of the two arms are connected to one another by way of a balance transistor, and wherein the source electrodes of the switching transistors are connected to a node which is discharged prior to the beginning of the reading cycle and, in order to evaluate a read-out signal, is discharged in a controlled manner such that the switching transistor across whose drain electrode occurs a change in voltage which produces the read-out signal, is rendered conductive.
2. Description of the Prior Art
In order to evaluate read-out signals of dynamic MOS memories, it is well known in the art to divide each bit line into two sub-portions, and to arrange a read-out amplifier circuit, designed as a flip-flop, between the two sub-portions. In this connection, one may refer to, for example, IEEE Journal of Solid-State Circuits, Vol. SC 7, No. 5, October 1972, Pages 336-340. A read-out amplifier circuit is constructed as a clocked flip-flop. The fundamental properties of this read-out amplifier reside in the symmetry thereof, the low dependence upon parameter fluctuations, and the automatic regeneration of the stored signals. Read-out amplifier circuits of this type are used, in particular, in MOS memories in which the individual storage cells consist of single-transistor storage cells.
A further development in MOS memory technology has resulted in an increasing rise in the storage density per storage module. This led to smaller read-out signals, and to component parameters which exhibit greater fluctuations. More suitable for evaluating read-out signals from MOS memories of this type, is an amplifier circuit, such as described, e.g. in IEEE Journal of Solid State Circuits, Vol. SC 8, No. 5, October 1973, Pages 310-318, and IEEE Journal of Solid State Circuits, Vol. 9, No. 2, April 1974, Pages 49-54. In this read-out amplifier circuit, the load transistors of the flip-flop serve only to pre-charge the sub-portions of the bit lines at the connection points between the load transistors and the switching transistors. During evaluation of a read-out signal, the load transistors remain blocked. If a signal voltage has set up on the sub-portions of a bit line, following the read-out of an item of information from a storage cell, the voltage is then slowly reduced at the connection point between the source electrodes of the switching transistors, In this manner, it is ensured that only one of the switching transistors, namely the switching transistor whose drain electrode is connected to the read-out signal, is rendered conductive. With this mode of operation, the amplification of the flip-flop is very high, and fluctuations in the geometry in the transistors and the capacitances of the bit line have virtually no significance. A disadvantage of this read-out amplifier circuit, however, resides in the relatively long evaluation time. Therefore, attempts have been made to reduce the voltage at the connection point of the source electrodes of the switching transistors in accordance with an optimum curve. Here, the curve is calculated to be such that one of the switching transistors is exactly at the blocking boundary, or alternatively operates in a weakly conductive state, in which the current is constant. This measure serves to shorten the resultant evaluation time. Nevertheless, the evaluation time is still relatively long.